==========================
sim - simulate the circuit
==========================

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    \begin{comment}

.. cmd:def:: sim
    :title: simulate the circuit



    .. code:: yoscrypt

        sim [options] [top-level]

    ::

        This command simulates the circuit using the given top-level module.


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        -vcd <filename>

    ::

            write the simulation results to the given VCD file


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        -fst <filename>

    ::

            write the simulation results to the given FST file


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        -aiw <filename>

    ::

            write the simulation results to an AIGER witness file
            (requires a *.aim file via -map)


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        -hdlname

    ::

            use the hdlname attribute when writing simulation results
            (preserves hierarchy in a flattened design)


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        -x

    ::

            ignore constant x outputs in simulation file.


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        -date

    ::

            include date and full version info in output.


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        -clock <portname>

    ::

            name of top-level clock input


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        -clockn <portname>

    ::

            name of top-level clock input (inverse polarity)


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        -multiclock

    ::

            mark that witness file is multiclock.


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        -reset <portname>

    ::

            name of top-level reset input (active high)


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        -resetn <portname>

    ::

            name of top-level inverted reset input (active low)


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        -rstlen <integer>

    ::

            number of cycles reset should stay active (default: 1)


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        -zinit

    ::

            zero-initialize all uninitialized regs and memories


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        -timescale <string>

    ::

            include the specified timescale declaration in the vcd


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        -n <integer>

    ::

            number of clock cycles to simulate (default: 20)


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        -noinitstate

    ::

            do not activate $initstate cells during the first cycle


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        -a

    ::

            use all nets in VCD/FST operations, not just those with public names


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        -w

    ::

            writeback mode: use final simulation state as new init state


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        -r <filename>

    ::

            read simulation or formal results file
                File formats supported: FST, VCD, AIW, WIT and .yw
                VCD support requires vcd2fst external tool to be present


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        -append <integer>

    ::

            number of extra clock cycles to simulate for a Yosys witness input


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        -summary <filename>

    ::

            write a JSON summary to the given file


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        -map <filename>

    ::

            read file with port and latch symbols, needed for AIGER witness input


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        -scope <name>

    ::

            scope of simulation top model


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        -at <time>

    ::

            sets start and stop time


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        -start <time>

    ::

            start co-simulation in arbitary time (default 0)


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        -stop <time>

    ::

            stop co-simulation in arbitary time (default END)


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        -sim

    ::

            simulation with stimulus from FST (default)


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        -sim-cmp

    ::

            co-simulation expect exact match


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        -sim-gold

    ::

            co-simulation, x in simulation can match any value in FST


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        -sim-gate

    ::

            co-simulation, x in FST can match any value in simulation


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        -assert

    ::

            fail the simulation command if, in the course of simulating,
            any of the asserts in the design fail


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        -q

    ::

            disable per-cycle/sample log message


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        -d

    ::

            enable debug output

.. raw:: latex

    \end{comment}

.. only:: latex

    ::

        
            sim [options] [top-level]
        
        This command simulates the circuit using the given top-level module.
        
            -vcd <filename>
                write the simulation results to the given VCD file
        
            -fst <filename>
                write the simulation results to the given FST file
        
            -aiw <filename>
                write the simulation results to an AIGER witness file
                (requires a *.aim file via -map)
        
            -hdlname
                use the hdlname attribute when writing simulation results
                (preserves hierarchy in a flattened design)
        
            -x
                ignore constant x outputs in simulation file.
        
            -date
                include date and full version info in output.
        
            -clock <portname>
                name of top-level clock input
        
            -clockn <portname>
                name of top-level clock input (inverse polarity)
        
            -multiclock
                mark that witness file is multiclock.
        
            -reset <portname>
                name of top-level reset input (active high)
        
            -resetn <portname>
                name of top-level inverted reset input (active low)
        
            -rstlen <integer>
                number of cycles reset should stay active (default: 1)
        
            -zinit
                zero-initialize all uninitialized regs and memories
        
            -timescale <string>
                include the specified timescale declaration in the vcd
        
            -n <integer>
                number of clock cycles to simulate (default: 20)
        
            -noinitstate
                do not activate $initstate cells during the first cycle
        
            -a
                use all nets in VCD/FST operations, not just those with public names
        
            -w
                writeback mode: use final simulation state as new init state
        
            -r <filename>
                read simulation or formal results file
                    File formats supported: FST, VCD, AIW, WIT and .yw
                    VCD support requires vcd2fst external tool to be present
        
            -append <integer>
                number of extra clock cycles to simulate for a Yosys witness input
        
            -summary <filename>
                write a JSON summary to the given file
        
            -map <filename>
                read file with port and latch symbols, needed for AIGER witness input
        
            -scope <name>
                scope of simulation top model
        
            -at <time>
                sets start and stop time
        
            -start <time>
                start co-simulation in arbitary time (default 0)
        
            -stop <time>
                stop co-simulation in arbitary time (default END)
        
            -sim
                simulation with stimulus from FST (default)
        
            -sim-cmp
                co-simulation expect exact match
        
            -sim-gold
                co-simulation, x in simulation can match any value in FST
        
            -sim-gate
                co-simulation, x in FST can match any value in simulation
        
            -assert
                fail the simulation command if, in the course of simulating,
                any of the asserts in the design fail
        
            -q
                disable per-cycle/sample log message
        
            -d
                enable debug output